Upon completion of this course, the students will be able to
CO1 : illustrate the basic concepts in MOS and VLSI Technology. (K2)
CO2 :explain the design process of MOS Technology. (K2)
CO3 :develop subsystem and layout in VLSI circuits. (K3)
CO4 :discuss the concepts of Arithmetic building Blocks. (K2)
CO5 :model the digital system using Verilog HDL.(K3)
UNIT I MOS TECHNOLOGY9 Introduction to IC Technology-MOS and VLSI Technology -MOS transistors: Enhancement and Depletion mode transistor actions -Fabrication of NMOS, CMOS and BiCMOS transistors -Thermal aspects of processing -BiCMOS Technology -Production of E beam Masks-MOS electrical properties: IDS Vs VDS relationships, Threshold voltage-Trans conductanceVs Output conductance and Pull up to pull down ratio determination-BiCMOS Inverters-Latch up in CMOS circuits
UNIT II DESIGN PROCESSES AND SCALING EFFECTS 9 MOS and BiCMOS circuit design: Stick diagrams-Lambda based design rules-Layout diagrams -Scaling models-Scaling factors for device parameters-Limitations of scaling-Limits due to sub threshold currents-Limits on logic levels and supply voltage due to noise
UNIT III SUBSYSTEM DESIGN AND LAYOUT 9 Switch logic-GATE logic: Two input nMOS, CMOS and BiCMOS, NAND, AND, NOR gates -Combinational logic: Parity generator-Multiplexers-Clocked sequential circuits: Two phase clocking-Charge storage-Register elements and Shift register-System considerations: Bus lines arrangements-Pre-charged bus concepts-Power dissipation and Power distribution buses.
UNIT IVARITHMETIC BUILDING BLOCKS9Data path circuits, Architecture for ripple carry adders, carry look ahead adders, high speed adders, accumulators, Multipliers, dividers, Barrel shifters, speed and area tradeoff.
UNIT VSPECIFICATION USING VERILOG HDL9Design Methodologies –Modules –Instances –Test bench –Operators –Number Specification –Identifiers and Keywords –Data Types –Modules and Ports –Gate-Level Modeling -Dataflow Modeling –Behavioral Modeling-Gate level/Dataflow description of decoder, equality detector, comparator, priority encoder, half adder, full adder, Ripple R-2015 Curriculum & Syllabus for BE.EIE78carry adder, Behavioral modeling of D flip-flop, T flip-flop, Asynchronous counter, shift register L: 45 TOTAL: 45 PERIODS
1.D.A.Pucknell, K.Eshraghian, ―Basic VLSI Design‖, 3rd Edition, Prentice Hall of India, New Delhi, 2008.
2.Weste and Harris, ―CMOS VLSI DESIGN: A Circuit and Systems Perspective‖, 3rdEdition, Pearson Education, 2007. (4thReprint)
3.Samir Palnitkar, ―Verilog HDL, A Guide to Digital Design and Synthesis" 2nd Edition, Pearson Education, 2005.
1.Jan Rabaey, Anantha Chandrakasan, B.Nikolic, ―Digital Integrated Circuits: A Design Perspective‖, PHI, 2nd Edition, 2003
2.Wayne Wolf, ―Modern VLSI design‖, Pearson Education, 3rdEdition, 2007.
3.Uyemura J.P, ―Introduction to VLSI circuits and systems‖, Wiley, 2002.
4.Ciletti, ―Advanced Digital Design with the Verilog HDL‖, Prentice Hall of India, 20
- Teacher: BABITHA THANGAMALAR J